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1/13 rev. a structure silicon mon olithic integrated circuit product 4k8 bit electrically erasable prom part number BU9890GUL-W physical dimension fig.-1vcsp50l1 block diagram fig.-2 use general purpose features ?4k words 8 bits architecture serial eeprom ?wide operating voltage range (1.7v3 .6v) ? two wire serial interface ? self-timed write cycle with automatic erase ? 32 byte page write mode ? low power consumption write 3.3v 0.6ma (typ.) read 3.6v 0.6ma (typ.) standby 3.6v 0.1a (typ.) ? data security write protect feature (wp pin) inhibit to write at low v cc ? wlcsp 6pin package ? high reliability fine pat tern cmos technology ? endurance : 100,000 erase/write cycles ? data retention : 40 years ? filtered inputs in scl?sda for noise suppression ? initial data ffh in all address ? pull-up resistor in puts in scl?sda absolute maximum rating (ta=25 parameter symbol rating unit supply voltage v cc -0.36.5 v power dissipation 220 *1 mw storage temperature tstg -65125 operating temperature topr -4085 terminal voltage -0.3vcc+1.0 *2 v *1 degradation is done at 2.2mw /*1 for operation above 25 *2 maximum value of terminal voltage is below 6.5v. recommended operating condition parameter symbol rating unit supply voltage write vcc 2.73.3 v read 1.73.6 input voltage v in 0vcc v www.datasheet.co.kr datasheet pdf - http://www..net/
2/13 rev. a dc operating characteristics (unless otherwise specified ta=- 4085?v cc =1.73.6v) parameter symb ol specification unit test condition min. typ. max. ? h ? input voltage1 v ih1 0.7v cc vcc+1.0 v 2.5vQvccQ3.6v ? l ? input voltage1 v il1 -0.3 0.3v cc v 2.5vQvccQ3.6v ? h ? input voltage2 v ih2 0.8v cc vcc+1.0 v 1.8vQvcc2.5v ? l ? input voltage2 v il2 -0.3 0.2v cc v 1.8vQvcc2.5v ? h ? input voltage3 v ih3 0.9vcc vcc+1.0 v 1.7vQvcc1.8v ? l ? input voltage3 v il3 -0.3 0.1vcc v 1.7vQvcc1.8v ? l ? output voltage1 v ol1 0.4 vi ol =3.0ma2.5vQvccQ3.6vsda ? l ? output voltage2 v ol2 0.2 vi ol =0.7ma1.7vQvcc2.5vsda input leakage current i li -1 1 av in =0vv cc , (wp, test) pull-up resistor i li2 6 1014 k(scl, sda) output leakage current i lo -1 1 av out =0vv cc sda operating current i cc1 4. ma v cc =3.3v,f scl =400hz t wr =5ms byte write page write i cc2 1.7 ma v cc =3.6v,f scl =400hz random read current read sequential read standby current i sb 2.0 a v cc =3.6v,sda,scl=v cc wp=gnd this product is not designed for protection against radioactive rays. memory cell characteristics(ta=25vcc=1.73.6v parameter specification unit min. typ. max. write/erase cycle *1 100,000 cycle data retention *1 40 year *1:not 1 00 tested www.datasheet.co.kr datasheet pdf - http://www..net/
3/13 rev. a fig.-1 physical dimension unit : mm 9890 product name : BU9890GUL-W lot.no www.datasheet.co.kr datasheet pdf - http://www..net/
4/13 rev. a block diagram fig.-2 block diagram vcc gnd sda scl wp test 32 kbit eeprom array address decoder slave?word address register data register contorol logic high voltage gen. v cc level 12bit 12bit 8bit ack start stop test pin connect with gnd www.datasheet.co.kr datasheet pdf - http://www..net/
5/13 rev. a pin configuration pin name land no. pin name i/o functions b3 vcc - power supply b2 gnd - ground 0v b1 test in test pin connect with gnd a3 wp in write protect input a2 scl in serial clock input a1 sda in/out slave and word address, serial data input, serial data output b a 1 3 a1 b1 test gnd vdd wp scl sda 2 a3 a2 b2 b3 www.datasheet.co.kr datasheet pdf - http://www..net/
6/13 rev. a ac operating characteristics ( unless otherwise specified ta=-4 085?v cc =1.73.6v) parameter symbol f-mode 2.5vQv cc Q3.6v standard-mode 1.7vQv cc Q3.6v unit min. typ. max. min. typ. max. clock frequency fscl 400 100 khz data clock high period thigh 0.6 4.0 s data clock low period tlow 1.2 4.7 s sda and scl rise time *1 tr 0.3 1.0 s sda and scl fall time *1 tf 0.3 0.3 s start condition hold time thd:sta 0.6 4.0 s start condition setup time tsu:sta 0.6 4.7 s input data hold time thd:dat 0 0 ns input data setup time tsu:dat 100 250 ns output data delay time tpd 0.1 0.9 0.2 3.5 s output data hold time tdh 0.1 0.2 s stop condition setup time tsu:sto 0.6 4.7 s bus free time tbuf 1.2 4.7 s write cycle time twr 5 5 ms noise spike width (sda and scl) ti 0.1 0.1 s wp hold time thdwp0 0 ns wp setup time tsuwp 0.1 0.1 s wp high period thighwp 1.0 1.0 s *1ot 10 0 tested www.datasheet.co.kr datasheet pdf - http://www..net/
7/13 rev. a synchronous data timing sda (in) scl sda (out) t hd :sta t hd :dat t su :dat t buf t pd t dh t low t high t r t f sda scl t su :sta t su :sto t hd :sta start bit stop bit sda data is latched into the chip at the rising edge of s cl clock. output date toggles at the falling edge of scl clock. write cycle timing sda d0 ack t wr scl write data(n) stop condition start condition fig.-5 write cycle timing fig.-4 synchronous data timing www.datasheet.co.kr datasheet pdf - http://www..net/
8/13 rev. a wp timing for the write operation, wp must be "low" during the period of time from the rising edge of the clock which takes in d0 of first byte until the end of t wr. ( see fig.-6(a) ) during this period, write operation is canceled by setting w p "high". see fig.-6(b) in the case of setting wp "high" during t wr, write operation is stopped in the middle and the data of accessing address is not guaranteed. please wri te correct data again in the case. scl sda wp fig.-6(a) wp timing of the write operation wp stop bit t high : wp d1 d0 ack ack data ( 1 ) data ( n ) scl wp sda d1 d0 ack ack data ( 1 ) data ( n ) t su wp fig.-6(b) wp timing of the write cancel operation www.datasheet.co.kr datasheet pdf - http://www..net/
9/13 rev. a device operation start condition (recognition of start bit) ?all commands are proceeded by the start condition, which is a high to low transition of sda when scl is high. ?the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see fig.-4 synchronous data timing stop condition (recognition of stop bit) ?all commands must be terminated by a stop condition, which is a low to high transition of sda when scl is high. see fig.-4 synchronous data timing notice about write command ?in the case that stop condition is not excuted in wr ite mode, transfered data will not be written in a memory. device addressing ?following a start condition, the master output the slave addre ss to be accessed. ?the most significant four bits of the slave address are the ? device type indentifier, ? for this device it is fixed as ? 1010 ? and next three bit set to ? 000 ? . ? the last bit of the stream (r/w read/write) determines the op eration to be performed. when set to ? 1 ? , a read operation is selected ; when set to ? 0 ? , a write operation is selected. r/w set to ? 0 ? ? ? ? ? ? ? ? ? write (including word address input of random read) r/w set to ? 1 ? ? ? ? ? ? ? ? ? read ?? write protect (wp) when wp pin set to v cc (h level), write protect is set for 4,096 words (all address). when wp pin set to gnd(l level), it is enable to write 4,096 wo rds (all address). either control this pin or connect to gnd ( or vcc). it is inhi bited from being left unconnected. www.datasheet.co.kr datasheet pdf - http://www..net/
10/13 rev. a acknowledge ?acknowledge is a software convention used to indicate successf ul data transfers. the transmitter device will rele ase the bus after transmitting eight bits. (when inputting the slave address in the write or read operatio n, transmitter is -com. when outputting the data in the read operation, it is this devi ce.) ?during the ninth clock cycle, t he receiver will pull the sda l ine low to acknowledge that the eight bits of data has been received. (when inputting the slave address in the write or read operatio n, receiver is this device. when outputting the data in the read operation, it is -com.) ?the device will respond with an acknowledge after recognition of a start condition and its slave address (8bit). ?in the write mode, the device w ill respond with an acknowledge , after the receipt of each subsequent 8-bit word (word address and write data). ?in the read mode, the device w ill transmit eight bit of data, release the sda line, and monitor the line for an acknowledge. ?if an acknowledge is detected, and no stop condition is genera ted by the master, the device will continue to transmit the data. if an acknowledge is not detected, the de vice will terminate f urther data transmissions and await a stop condition before returning to the standby mod e. (see fig.-7 acknowledge response from receiver) sda scl 189 acknowledge signal (ack signal) start condition (start bit) from-com ic output data sda -com output data) fig.-7 acknowledge response from receiver www.datasheet.co.kr datasheet pdf - http://www..net/
11/13 rev. a byte write w r i t e s t a r t r / w a c k s t o p 1st word address wp sda line a c k a c k data a c k slave address 10 0 10 0 0 wa 11 d7 d0 2nd word address *** * : don ? t care wa 0 * by using this command, the data is programed into the indicate d word address. when the master generates a stop condition, the device begins the internal write cycle to the nonvolatile memory array. w r i t e s t a r t r / w a c k s t o p 1st word address? data(n) wp sda line a c k a c k data(n+31) a c k slave address 10 0 10 0 0 wa 11 d0 d7 d0 *** 2nd word address? a c k * : don ? t care wa 0 * this device is capable of thirty -two byte page write operation . when two or more byte data are inputted, the five low order ad dress(wa4wa0) bits are in ternally incremented by one after the receipt of each word. the seven higher order bits of the address(wa4wa0) remain constant. fig.-8 byte write cycle timing fig.-9 page write cycle timing www.datasheet.co.kr datasheet pdf - http://www..net/
12/13 rev. a 0 0d7 1 1 0 0 r e a d s t a r t r / w s t o p data sda line slave address 0d0 a c k a c k in case that the previous operation is random or current read ( which includes sequential read respectively), the internal address counter is increased by one from the last accessed address (n). thus current read outputs the data of the next word addres s (n+1). if the last command is byte or page write, the internal address counter stays at the last address (n). thus current read outputs the data of the word address (n). if an acknowledge is detected, and no stop condition is genera ted by the master (-com), the device will continue to trans mit the data. it can transmi t all data (32kbit 4096word) if an acknowledge is not detect ed, the device will terminate f urther data transmissions and await a stop condition before returning to the standby mode . note) if an acknowledge is detected with "low" level, not "high " level, command will become sequential read. so the device transmits the next data, read is not terminated. in the case of terminating read, input acknowledge with "high" always, then input stop condition. w r i t e s t a r t r / w a c k s t o p 1st word address? sda line a c k a c k data(n) a c k slave address 1 0 0 1 0 0 0 wa 11 d7 d0 *** 2nd word address? a c k * : don ? t care s t a r t slave address 1 0 0 1a1 a2 r / w r e a d a0 wa 0 * random read operation allows the master to access any memory l ocation indicated word address. if an acknowledge is detected, and no stop condition is genera ted by the master (-com), the device will continue to tran smit the data. it can transmit all data (32kbit 4096word) if an acknowledge is not detect ed, the device will terminate f urther data transmissions and await a stop condition before returning to the standby mode . note) if an acknowledge is detected with "low" level, not "high " level, command will become sequential read. so the device transmits the next data, read is not terminated. in the case of terminating read, input acknowledge with "high" always, then input stop condition. fig.-11 random read cycle timing fig.-10 current read cycle timing www.datasheet.co.kr datasheet pdf - http://www..net/
13/13 rev. a r e a d s t a r t r / w a c k s t o p data(n) sda line a c k a c k data(n+x) a c k slave address 10 0 10 0 0 d0 d7 d0 d7 if an acknowledge is detected, and no stop condition is gener ated by the master (-co m), the device will continue to transmit the data. it can tran smit all data (32kbit 4096word) if an acknowledge is not detect ed, the device will terminate f urther data transmissions and await a stop condition before returning to the standby mode . the sequential read operation ca n be performed with both curre nt read and random read. note) if an acknowledge is detected with "low" level, not "high " level, command will become sequential read. so the device transmits the next data, read is not terminated. in the case of terminating read, input acknowledge with "high" always, then input stop condition. fig.-12 sequential read cycle timing current read www.datasheet.co.kr datasheet pdf - http://www..net/
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